Semiconductor diode and method for the production thereof

ABSTRACT

In a semiconductor system  20  made up of multiple sublayers, a sublayer over the largest part of a cross-sectional area BC in the interior of the semiconductor system borders immediately on the first sublayer, while bordering on a second sublayer only in a comparatively narrow edge region of the cross-sectional area. The semiconductor system is characterized by a low bulk resistance and a high breakdown voltage in the edge region. In addition, a method for manufacturing this semiconductor system is specified.

FIELD OF THE INVENTION

The present invention relates to a semiconductor system.

BACKGROUND INFORMATION

German Patent Document No. 43 20 780 refers to a semiconductor diode, inwhich the doping profile at the edges of the diode deviates from thedoping profile at the center. This can be used so that in reverse-biasedoperation the voltage breakdown, which sets in at breakdown voltage UZ,occurs only in the central part of the diode and not at the edge. Thisresults in a high robustness in operation since no avalanche breakdowncan occur at the chip edges.

German Patent Document No. 43 20 780 further refers to a semiconductorsystem having a p-n junction, in particular a diode, which takes theform of a chip having an edge region, which is constructed of a firstlayer of a first conductivity type and a second layer of the oppositeconductivity type, the second layer being made up of at least twosublayers. In this instance, the first sublayer has a first dopantconcentration, while the second sublayer has a second dopantconcentration which is lower than the first dopant concentration.Together with the first layer, both sublayers form a p-n junction, thep-n junction of the first layer with the first sublayer being formedexclusively in the interior of the chip and the p-n junction between thefirst layer and the second sublayer being formed in the edge region ofthe chip.

The available semiconductor system has the distinction of having a highrobustness in operation since, due to the special form of the dopingprofile in the edge region, no voltage breakdown occurs in the edgeregion in reverse-biased operation of the semiconductor system. It isdisadvantageous, however, that this semiconductor system has arelatively high electrical resistance as a result of its lightly dopedmiddle layer. This high electrical resistance causes an undesiredvoltage drop, which has an adverse effect particularly in breakdownoperation. This is all the more pronounced the higher the breakdownvoltage UZ of the semiconductor system. For this reason, thissemiconductor system is not suited for higher breakdown voltages, asrequired, for example, for use in a 42 volt vehicle electrical system.

SUMMARY OF THE INVENTION

The semiconductor system according to the present invention avoids thisdisadvantage due to its special layer structure. Hence it is excellentlysuited for use in vehicle electrical systems that operate at a voltagehigher than 24 volts. Furthermore, the semiconductor system according tothe present invention is characterized by a lower reverse current, amore robust behavior in the event of temperature changes as well as ahigher pulse strength. The lower reverse current and the higher pulsestrength are due to the fact that, in the semiconductor system accordingto the present invention, the space charge region at the edge region ofsemiconductor system 10 extends further than in its central region,thereby lowering the electric field strength at the surface of the edgeregion. As a consequence of the low reverse currents, it is alsopossible to dispense with a removal of the damage zone, for example byetching.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a known semiconductor system in a schematic sectional view.

FIG. 2 shows a first exemplary embodiment of a semiconductor systemaccording to the present invention in a schematic sectional view.

FIG. 3 shows a second exemplary embodiment of a semiconductor systemaccording to the present invention.

FIG. 4 a shows a comparison of the saw trench geometry between a knownsemiconductor system.

FIG. 4 b shows a semiconductor system according to the present inventionin detail in a sectional view.

FIG. 5 shows a diagram of the schematic representation of the dopingprofiles of the known semiconductor system and of the semiconductorsystem according to the present invention in comparison along sectionAB.

FIG. 6 shows a further exemplary embodiment of the present invention, inwhich contiguous layers of the semiconductor system are made of the samedoping type.

DETAILED DESCRIPTION

FIG. 1 first shows a known semiconductor system 10 made up of severalvariably doped layers 1, 2, 3, 4. Layers 1, 2, 4 are n-doped atdifferent concentrations, while layer 3 is a p-doped layer. The outersurfaces of layers 3 and 4 are coated with contact layers 5, 6 made ofmetal. This semiconductor system 10 is a diode for example. Togetherwith the n-doped layers 1, 2, p-doped layer 3 forms a p-n junction.Since higher n-doped layer 2 is essentially found only at the center ofthe semiconductor system, the doping profile at the edges of the diodediffers from the doping profile in the central region of the diode.Hence, in reverse-biased operation of the diode, a voltage breakdown ata breakdown voltage UZ essentially only occurs in the central region ofthe diode and not in its edge region. To be sure, this results in a highrobustness in operation since no avalanche breakdown can occur in theedge region of the diode. It is particularly disadvantageous forapplications of the diode at higher voltages, however, that the diodehas a comparatively high electrical resistance as a consequence ofweakly n-doped layer 1. This resistance causes an undesired voltagedrop, which has an adverse effect particularly in breakdown operation.This is all the more pronounced the higher the breakdown voltage UZ ofthe diode. For this reason, a conventional diode of this type is notsuited for higher breakdown voltages, as are required, for example, foruse in vehicle electrical systems that have a 42 V operating voltage.The proposed invention eliminates this disadvantage.

In a schematic sectional view, FIG. 2 shows as the first exemplaryembodiment of the present invention a semiconductor system 20 made up ofmultiple sublayers featuring different doping. The starting point is aweakly n-doped semiconductor substrate, which forms a first sublayer 1.In the central region of this semiconductor substrate, a second n-dopedsublayer 2, which, however, does not extend to the edge regions ofsublayer 1, is introduced from the upper side. Likewise from the upperside, a third p-doped sublayer 3 extends to the n-doped sublayer 2 inthe central region and to the n-doped sublayer 1 in the edge region ofsemiconductor system 20. The boundary regions between sublayers 3 and 2and between 3 and 1 form the p-n junctions. 5 and 6 designate metalliccontact layers that are deposited on the outer surfaces of sublayers 3and 4. Since the n-doping concentration of sublayer 2 is greater thanthe n-doping concentration of sublayer 1, the breakdown voltage UZM ofthe p-n junction 3-2 lying in the central region of semiconductor system20 between sublayers 3 and 2 is smaller than the breakdown voltage UZRof the p-n junction 3-1 lying in the edge region of semiconductor system20 between sublayers 3 and 1.

This ensures that also in the semiconductor system according to thepresent invention a breakdown can occur only in the central region ofsemiconductor system 20 and not in its edge region. As a consequence ofthe charge neutrality, the space charge region in the edge region ofsemiconductor system 20 extends further than in its central region. Thishas the consequence that the electric field strength is reduced at thesurface of the edge region of semiconductor system 20. Thisadvantageously results in a lower reverse current and a higher pulsestrength. As a consequence of the low reverse current, it is alsopossible advantageously to dispense with a removal of the damage zone,for example by an additional etching process. From the backside ofsemiconductor system 20 a heavily n-doped further sublayer 4 extends outto n-doped sublayer 2 and lightly n-doped sublayer 1. In contrast to theconventional semiconductor system 10 represented in FIG. 1, a lightlyn-doped sublayer 1 remains only in a narrow edge region between then-doped sublayers 3 and 4. In the central region of semiconductor system20, therefore, the n-doping concentration is higher than the basicdoping of first sublayer 1 in the semiconductor system. The avoidanceaccording to the present invention of a lightly n-doped sublayer 1between sublayers 3 and 4 in semiconductor system 20 achieves asignificantly lower bulk resistance than in a conventional semiconductorsystem. In the event of a breakdown, this advantageously results in alower voltage drop.

A further exemplary embodiment of the semiconductor system of thepresent invention is represented in a schematic cross-sectional view inFIG. 3. In contrast to semiconductor system 20 represented in FIG. 2,this semiconductor system 30 has no depression in its edge region. Thismakes it possible to achieve an even higher breakdown voltage UZR in theedge region of semiconductor system 30 with all the associatedadvantages such as a lower reverse current and a higher pulse strength,while maintaining the same overall thickness of semiconductor systems20, 30.

A further exemplary embodiment of the semiconductor system according tothe present invention is represented in FIG. 6. In contrast tosemiconductor systems 20 and 30 in FIG. 2 and FIG. 3, sublayer 2 is madeof the same doping type as sublayer 3.

Furthermore, exemplary embodiments are conceivable in which the startingmaterial of sublayer 1 is not doped homogeneously. Rather, this sublayer1 is deposited as an epitaxy layer on an already heavily doped sublayer4.

In the following, a particularly advantageous manufacturing method formanufacturing a semiconductor system having the layer structurerepresented in FIG. 2 is described with reference to FIG. 2. Themanufacture of a diode having a Zener voltage UZ of approximately 50volts is described as an example. Of course, using the method accordingto the present invention, diodes may be provided that are for higher orlower Zener voltages. Thus it is possible, for example, to produce aZener voltage of approximately 20 volts by a simple variation of thedoping profile. One starts from a semiconductor substrate made ofsilicon having a thickness of approximately 180 μm and an n-doping ofapproximately 1*10¹⁶ cm⁻³, which forms first sublayer 1 of semiconductorsystem 20. This sublayer 1 is doped with phosphorus on the upper andlower side. This can be done advantageously using ion implantation,doping glasses, doping foils or, particularly suitably, by a methodreferred to as the APCVD method (atmospheric pressure chemical vapordeposition). In a particularly simple and economical way, the doping ofsublayer 1 by phosphorus atoms can also occur in a gas phase. To thisend, sublayer 1 is exposed to an atmosphere of POCl₃ at an elevatedtemperature. Temperatures approximately between 830° C. and 890° C. aresuitable for this purpose, particularly a temperature of 870° C.Following the doping process, the glass layers remaining on thesemiconductor substrate are removed by an etching process using dilutedhydrofluoric acid. If doping glasses are used for doping, then thedeposition of the doped glasses is followed by a so-called drive-in stepto drive the doping atoms into the semiconductor substrate to be doped,that is, the first sublayer 1. A drive-in step of 20 to 40 minutes,particularly 30 minutes, has proved to be especially favorable. Thisdrive-in step is suitably performed at an elevated temperature ofapproximately 1200 to 1300, particularly of 1265° C. Following thisdoping step, the integral over the concentration of phosphorus atoms,the dose, amounts on each doped side of first sublayer 1 toapproximately 2*10¹⁶ cm⁻² The penetration depth of the phosphorus atomsinto the n-doped semiconductor material of first sublayer 1 isapproximately 5-15 micrometers. In the case of a PoCl₃ gas phasedeposition it is less than approximately 1 micrometer. Subsequently, theupper side of doped first sublayer 1 is structured. This can occur in aparticularly advantageous manner by saw cuts into the upper side using adiamond saw or by water-supported laser cutting. The sawing depth ST(FIG. 4) is approximately 1-35 micrometers. As a rule, the sawing depthST is suitably chosen in such a way that it is greater than thepenetration depth of the phosphorus atoms in the surface of sublayer 1.A suitable choice of the sawing depth ST can substantially influence thelateral outdiffusion of the phosphorus layer or the phosphorusconcentration and thus the breakdown field strength in the edge regionof semiconductor system 20 during the subsequent diffusion process. Thewidth SB of the saw blade used also depends on the desired sawing depthand the subsequent diffusion process. Saw widths SB (FIGS. 1, 2, 4 b, 6)in the order of approximately 300 micrometers are typical. Followingthis mechanical structuring process, a further diffusion process isperformed, in which the n-dopants are driven into the semiconductorsubstrate. This drive-in may occur in an oxidizing atmosphere, suitablyin dry or also in wet oxygen. As a variation, a diffusion in anatmosphere made of pure nitrogen or a nitrogen-oxygen mixture ispossible as well. This diffusion process is also carried out at a hightemperature between 1200 and 1300° C., particularly at a temperature of1265° C. The semiconductor substrate is exposed to this temperature forapproximately 140 hours. During the diffusion process, the semiconductorsubstrate is positioned on a suitable carrier, which may be made of SiCor a similar temperature-resistant material. Following the previouslydescribed diffusion process, the layer of SiO₂ thereby produced on thesurface of the semiconductor substrate is etched off again. In order toincrease the efficiency of the method, in principle multiplesemiconductor substrates can be piled into a stack and be jointlyexposed to the diffusion process. For this purpose, so-called neutralfoils (neutral preforms) are suitably arranged between the individualsemiconductor substrates. These neutral foils contain antitack agentssuch as pellets made of SiC or Al₂O₃ for example and thus prevent thesemiconductor substrates from sticking together. Following a successfulconclusion of the diffusion process, the individual semiconductorsubstrates are again separated from one another using dilutedhydrofluoric acid. In a subsequent further diffusion process, anadditional sublayer 3 is now applied which is p-doped. At the same time,the concentration of the doping atoms in sublayer 4 is to be increasedfurther. In principle, all doping methods familiar to one skilled in theart are suited for this purpose. The use of so-called doping foils,however, is particularly advantageous. For this purpose, alternatelyp-doping foils and n-doping foils together with the semiconductorsubstrates are again piled up into stacks and heated together. Thisprocess step requires a time of approximately 30 hours at a temperatureof 1265° C. Especially advantageous in this implementation of the methodis the fact that sublayers 3 and 4 can be produced together in onesingle diffusion step. As already described above, following theconclusion of the diffusion step, the individual semiconductorsubstrates are again separated from one another using dilutedhydrofluoric acid.

The diffusion profile in the central region (compare step AB in FIG. 2)of a diode manufactured in the previously described manner isrepresented in the diagram in FIG. 5 (curve shape II). This diagramshows the doping concentration as a function of the distance x. As aspecial feature it may be pointed out that the minimum dopingconcentration in this diode is greater than the basic doping of thesemiconductor substrate, that is, the doping of first sublayer 1 in FIG.2 or 3.

In contrast to the conventional structure of a semiconductor systemaccording to FIG. 1, in which the sawing-in process only occurs afterthe diffusion of n-doped sublayer 2, in the approach according to theexemplary embodiment and/or exemplary method of the present invention asmaller sawing depth ST can be chosen than in the conventionalsemiconductor system. Since the portion of first sublayer 1 stillremaining is greater than in the conventional design approach, it ispossible to achieve higher breakdown voltages UZR in the edge region ofthe semiconductor structure according to the present invention. If, asin the conventional semiconductor structure, it is not possible toselect a sawing depth that is sufficiently small because the sawing-inprocess occurs only after the first diffusion treatment of n-dopedsublayer 2, p-doped third sublayer 3 diffuses together with n-dopedsublayer 4 in the edge region of the semiconductor system. This,however, greatly reduces the breakdown voltage UZR.

In a further exemplary method according to the present invention, thepreviously described joint diffusion of p-doped sublayer 3 and n-dopedsublayer 4 can also be split up into two partial steps. To this end, thedopants are initially introduced in the first partial step and are thendriven in further in a second partial step. Again, the doping anddiffusion methods already described above can be used for this purpose.In particular, it is possible to use stack diffusion and diffusion inboots or a combination of both methods.

Subsequently, the upper side and the lower side of the semiconductorsubstrate are each provided with one contact layer 5, 6 made of metal(FIG. 2). However, a complex layer sequence made of several metals maybe deposited for this purpose. The combination chromium, nickel, silver,for example, is particularly well suited.

Following the metallization of the contact regions of the semiconductorsubstrates, the individual semiconductor systems, that is, diodes in theexemplary embodiment described, are separated from one another forexample by sawing using a diamond saw. Customarily, saw blades of awidth of 40 micrometers are used for this purpose. This sawing processyields individual diodes, which are normally additionally equipped witha housing. The diode is soldered into the housing and is protected byit.

In unfavorable sawing condition that depend, for example, on the grainsize of the diamond splinters of the saw, the rotational speed and thefeed rate, the separation of the semiconductor substrates with the aidof a diamond saw can cause faulty crystal zones in the edge region ofsemiconductor system 20, 30, 60. These faulty crystal zones in turn giverise to undesired additional reverse currents in the operation of thesemiconductor system. Thus the faulty crystal zones are normally removedin an additional method step, by etching for example. In semiconductorsystem 20, 30, 60 according to the exemplary embodiment and/or exemplarymethod of the present invention, however, breakdown voltage UZR in theedge region of the semiconductor system is significantly higher than ina conventional semiconductor system such as the one according to FIG. 1.Hence the ratio of the breakdown voltage UZR at the edge region ofsemiconductor system to the breakdown voltage UZM in the central regionof the semiconductor system is also significantly higher. This has theconsequence that in the semiconductor system configured according to thepresent invention, the reverse current originating from the possiblyfaulty edge region is significantly lower.

Thus in most cases it is also not necessary to remove the faulty crystalzones (damage zones) in the edge region of the semiconductor systemaccording to the present invention. This results in a simplification ofthe manufacturing method and thus to an additional reduction in cost.

If the faulty edge regions are removed nevertheless, as is described inthe following, a yet significantly lower reverse current is achieved.Wet-chemical etching methods using KOH, gas phase etching or similarmethods lend themselves for removing the faulty edge regions of thesemiconductor system. However, since in contrast to conventionalsemiconductor systems only very shallow sawing trenches are required, awet-chemical etching method using KOH or a comparable etching solutionlends itself especially well. In a conventional semiconductor systemaccording to FIG. 1, the required sawing trench is particularly deep andnarrow. For example, the ratio of sawing width SB to sawing depth ST is2.5. In semiconductor system 20 according the present invention as shownin FIG. 2, by contrast, the ratio of sawing width SB to sawing depth STis 15 for example. These ratios are represented in FIG. 4 by partialfigures FIG. 4 a and FIG. 4 b. In both figures, an enlarged detail of anedge region of a semiconductor system is shown in cross section. Thesemiconductor substrate is identified by 7. Reference numeral 8designates a solder layer. Reference numeral 9 indicates a heat sinkmade of copper for example. The sawing width is indicated by the lettercombination SB and the sawing depth by ST.

A conventional semiconductor system is represented in FIG. 4 a, whileFIG. 4 b shows a semiconductor system according to the presentinvention. As FIG. 4 b clearly shows, in the semiconductor systemaccording to the present invention, solder layer 8 completely fills thesawing trench indicated by sawing width SB and sawing depth ST. This hasthe advantage that in a subsequent wet-chemical etching process contactlayer 5 or the semiconductor material below it are no longer attacked inthe region of the sawing trench since they are completely covered bysolder layer 8. Moreover, a sawing trench filled completely with ductilesolder material offers the advantage that the semiconductor substrate isrelieved mechanically if as a result of temperature change stresses,pressure and/or shearing forces are exerted on the semiconductor system.In addition, the dissipation of heat from the semiconductor substrate isfurther improved. The advantages described above, by contrast, cannot beobtained with the embodiment of a conventional semiconductor systemshown in FIG. 4 a.

A further exemplary embodiment of a semiconductor system 30 according tothe present invention is represented schematically in FIG. 3 in crosssection. In this case, a depression of the semiconductor substrate inthe edge region was dispensed with completely. This allows for an evenhigher breakdown voltage UZR in the edge region, while maintaining thesame thickness of the semiconductor substrate as in semiconductor system20 in FIG. 2. This results in further advantages such as a lower reversecurrent and a greater pulse strength. The structural design and themanufacturing method are practically identical as in the exemplaryembodiment of the present invention described above with reference toFIG. 2. The structuring of n-doped layer 2, however, may also occuradvantageously by method steps known from conventional photolithographyand planar technology. These method steps include in particular thesteps of thermal oxidation, photo-resist coating, pre-curing, exposureand curing of the photo-resist, etching of the contact windows andstripping of the photo-resist. In sufficiently thick thermal oxidelayers, the oxide layer may advantageously also act as a diffusionbarrier for the phosphorus atoms to be introduced into the semiconductorsubstrate. In the high diffusion temperatures used, the oxide layer musthave a thickness of 3-5 micrometers. The structuring occurs in such away that in the central region of the semiconductor substrate no oxidelayer remains, while at its edge R, however, an oxide layer does remain.This structuring step is followed by the process steps already describedabove, beginning with the doping of n-doped layer 2.

A further exemplary embodiment of a semiconductor system 60 according tothe present invention is represented schematically in a cross section inFIG. 6. Deviating from the exemplary embodiment of semiconductor system20 in FIG. 2, sublayer 2 is doped with boron instead of phosphorus. Incontrast to semiconductor system 20, reverse current UZM at the centerof the semiconductor system is determined by the junction betweensublayers 2-4 and not by the junction between sublayers 3-2.

In principle, exemplary embodiments are possible as well in whichstarting material 1 is not available in homogeneously doped form butrather as an epitaxy layer that is deposited on an already heavily dopedsubstrate 4.

Even if semiconductor diodes, particularly Zener diodes, are representedin the figures, the disclosure according to the exemplary embodimentand/or exemplary method of the present invention can also be applied toother semiconductor systems which have a p-n junction between a heavilydoped p-layer and a heavily doped n-layer followed by a more weaklydoped n-layer. Likewise semiconductor components are possible in whichall p-layers and n-layers are interchanged.

The List of Reference Characters is as follows:

-   1 Doped layer-   2 Doped layer-   3 Doped layer-   4 Doped layer-   5 Contact layer-   6 Contact layer-   7 Semiconductor substrate-   8 Solder layer-   9 Heat sink-   10 Semiconductor system-   20 Semiconductor system-   30 Semiconductor system-   60 Semiconductor system-   SB Sawing width-   ST Sawing depth-   R Edge

1. A semiconductor system having a p-n junction, comprising: a substratehaving an edge region, which is made up of a first layer of a firstconductivity type and a second layer of an opposite conductivity type,the second layer being made up of at least two sublayers, wherein: thefirst sublayer has a first dopant concentration, the second sublayer hasa second dopant concentration that is lower than the first dopantconcentration, both sublayers together with the first layer form a p-njunction, the p-n junction of the first layer with the first sublayerbeing formed exclusively in an interior of the chip and the p-n junctionbetween the first layer and the second sublayer being formed in the edgeregion of the chip, the second layer includes a third sublayer having athird dopant concentration that is higher than the first dopantconcentration and significantly higher than the second dopantconcentration, the third sublayer over a largest part of itscross-sectional area in the interior of the semiconductor system bordersimmediately on the first sublayer, while bordering on the secondsublayer only in a comparatively narrow edge region of thecross-sectional area, wherein the first sublayer has a portion with athickness greater than the second sublayer.
 2. The semiconductor systemof claim 1, wherein the sublayers of the semiconductor system at leastone of touch in a central region of the semiconductor system, andoverlap in regions.
 3. The semiconductor system of claim 1, wherein adopant concentration in each of the sublayers is higher than a dopantconcentration in the sublayer forming the basic substrate.
 4. Thesemiconductor system of claim 1, wherein in its central region thesublayers form a first p-n junction between a p+-doped and an n+-dopedsemiconductor substrate.
 5. The semiconductor system of claim 1, whereinin its edge region the sublayers form a second p-n junction between ap+-doped and an n−-doped semiconductor substrate.
 6. The semiconductorsystem of claim 1, wherein it has in its edge region a wide, shallowsawing trench having a sawing width and a sawing depth, the sawing widthbeing at least one of greater than 80 micrometers and 100 micrometers,and wherein a ratio of the sawing width to the sawing depth has a valuegreater than
 3. 7. The semiconductor system of claim 1, wherein thesawing trench is completely filled with solder material so that the wallsurfaces of the sawing trench are covered by solder material and areprotected by this solder material.
 8. The semiconductor system of claim1, wherein the semiconductor system is part of a diode.
 9. Thesemiconductor system of claim 1, wherein a breakdown voltage in the edgeregion of the semiconductor system is significantly greater than abreakdown voltage in a central region of the semiconductor system. 10.The semiconductor system of claim 9, wherein the breakdown voltage inthe edge region is greater than the breakdown voltage approximately by afactor of 2 to
 7. 11. The semiconductor system of claim 1, wherein abulk resistance in a central region of the semiconductor system is lowerthan the bulk resistance in an edge region of the semiconductor.
 12. Asemiconductor system having a p-n junction, comprising: a substratehaving an edge region, which is made up of a first layer of a firstconductivity type and a second layer of an opposite conductivity type,the second layer being made up of at least two sublayers, the firstsublayer having a first dopant concentration and the second sublayerhaving a second dopant concentration that is lower than the first dopantconcentration, both sublayers together with the first layer forming ap-n junction, the p-n junction of the first layer with the firstsublayer of the second layer being formed exclusively in an interior ofthe chip and a p-n junction between the first layer and the secondsublayer being formed in an edge region of the chip, wherein a layerover a largest part of a cross-sectional area in the interior of thesemiconductor system borders immediately on the first layer, whilebordering on the second layer only in a comparatively narrow edge regionof the cross-sectional area, wherein the first sublayer has a portionwith a thickness greater than the second sublayer.
 13. A method formanufacturing a semiconductor system, comprising: manufacturing asemiconductor substrate of a first conductivity type forming a firstsublayer of the semiconductor system; doping the first sublayer on bothsides for forming two further sublayers of the same conductivity type asthe first sublayer but with different degrees of doping so that the twosublayers touch or overlap at most in a central region of thesemiconductor system; producing a fourth sublayer of an oppositeconductivity type by introducing a dopant into the sublayers and byincreasing the dopant concentration of the sublayer; covering outersurfaces of the sublayers with metallic contact layers; wherein thesemiconductor system has a p-n junction, including a substrate having anedge region, which is made up of the first layer of a first conductivitytype and a second layer of an opposite conductivity type, the secondlayer being made up of at least two sublayers, wherein: the firstsublayer has a first dopant concentration, the second sublayer has asecond dopant concentration that is lower than the first dopantconcentration, both sublayers together with the first layer form a p-njunction, the p-n junction of the first layer with the first sublayerbeing formed exclusively in an interior of the chip and the p-n junctionbetween the first layer and the second sublayer being formed in the edgeregion of the chip, the second layer includes a third sublayer having athird dopant concentration that is higher than the first dopantconcentration and significantly higher than the second dopantconcentration, the third sublayer over a largest part of itscross-sectional area in the interior of the semiconductor system bordersimmediately on the first sublayer, while bordering on the secondsublayer only in a comparatively narrow edge region of thecross-sectional area, wherein the first sublayer has a portion with athickness greater than the second sublayer.
 14. The semiconductor systemof claim 1, wherein p-doped and n-doped layers are interchanged.